Employing a bipolar-CMOS (complementary metal-oxide-semiconductor)-DMOS (double diffused metal-oxide-semiconductor) (hereinafter “BCD”) process, a power integrated circuit can be made for the applications in high voltage, high power and high integration density. In the BCD process, a high voltage N-type MOS (HV NMOS), such as a laterally double diffused N-type MOS (LDNMOS) or an extended drain N-type MOS (EDNMOS), is weak in the burn-out test of measuring the safe operation area (SOA).
Please refer to FIG. 1, which is a schematic diagram showing a cross-sectional view of a HV LDNMOS device 10 in the prior art. The HV LDNMOS device 10 includes two LDNMOS transistors 10A and 10B. For the following description, one of the LDNMOS transistors 10A and 10B will be referred although the discussion will refer to each.
The LDNMOS transistor 10A includes a workpiece 20. The workpiece 20 includes a P-doped silicon substrate 21, an N-doped buried layer (NBL) region 22, an epitaxially grown silicon layer 23, a doped high voltage N-well (HV NW) region 24, and field oxide (FOX) isolation regions 251 and 252. The P-doped silicon substrate 21 is provided and overlaid with the NBL region 22 formed by conventional methods. Following the formation of the NBL region 22, the epitaxially grown silicon layer 23 is deposited over the NBL region 22 and the P-doped silicon substrate 21 for formation of various doped regions. For example, following the formation of the epitaxially grown silicon layer 23, ion implantations are carried out to form the doped HV NW region 24 and a LOCOS process is carried out to form the FOX isolation regions 251 and 252.
Subsequent conventional processes are carried out to form a doped NW region 31, a P-doped base region 15, an N+ drain region 32, an N+ source region 16, a P+ base contact region 17 and a P+ substrate bulk region 33 in the workpiece 20. In addition, a gate structure 18, and metal contacts 351 and 352 are formed on an upper surface 201 of the workpiece 20.
Please refer to FIG. 2, which is a schematic diagram showing a top view of the HV LDNMOS device 10 in FIG. 1. The cross-sectional view in FIG. 1 is obtained from the cross section located at the cut line A-A′ in FIG. 2. As shown in FIG. 2, the metal contact 351 including a plurality of portions 3511, 3512, 3513, . . . , 3514 connects the N+ source region 16 to the P+ base contact region 17 for forming a source terminal. The metal contact 352 including a plurality of portions 3521, 3522, . . . , 3523 is connected to the N+ drain region 32 for forming a drain terminal. The P+ base contact region 17 is disposed between two N+ source regions 16. The gate structure 18 is disposed on the workpiece 20.
Please refer to FIG. 3 and FIG. 4, which are schematic diagrams showing a first transistor performance and a second transistor performance of the HV LDNMOS device 10 in FIG. 1, respectively. FIG. 3 shows a graph of the drain-source current Idd in Amperes (the y axis) tested over a range of the drain-source voltage Vds from 0 to 47 Volts (the x axis) in a condition that a range of the gate-source voltage Vgs is stepwise changed from 2 to 20 Volts at a voltage interval 1.6364 Volts, wherein the HV LDNMOS device 10 is configured as a circuit including the LDNMOS transistors 10A and 10B connected in parallel.
FIG. 4 shows a graph of the drain-source current Idd in Amperes (the y axis) tested over a range of the drain-source voltage Vds from 0 to 48 Volts (the x axis) in a condition that a range of the gate-source voltages Vgs is stepwise changed from 2 to 20 Volts at a voltage interval 1.6364 Volts, wherein the HV LDNMOS device 10 is the same as that for FIG. 3. The HV LDNMOS device 10 burns out at the operation point that the gate-source voltage Vgs and the drain-source voltage Vds are equal to 13.1 Volts and 48 Volts respectively. In view of FIG. 3 and FIG. 4, the SOA of the HV LDNMOS device 10 may has the characteristics: the safe operation range of the gate-source voltage Vgs is from 0 to 20 Volts, and the safe operation range of the drain-source voltage Vds is from 0 to 47 volts.
The HV LDNMOS device 10 has additional characteristics: the on-resistance Ron is 98 mΩ-mm2 at the operation point that the gate-source voltage Vgs and the drain-source voltage Vds are equal to 5 volts and 0.2 volts respectively; the threshold voltage is 1.39 Volts; the zero gate voltage drain current Ioff is 27 pA; the drain-source breakdown voltage Vbd is 58.7 Volts, which is the drain-source voltage at the operation point that the gate-source voltage Vgs and the drain current Idd are equal to 0 and 1 μA respectively; and the saturation drain current Idsat is 18 mA at the operation point that the gate-source voltage Vgs and the drain-source voltage Vds are equal to 20 Volts and 40 Volts respectively.
The HV LDNMOS device 10 can be used in power electronic applications such as the LCD driver, the power conversion and the consumer audio. The high voltage stress and the high current stress often occur in the switching circuits of these applications. Therefore, it is necessary to further improve the SOA of the HV LDNMOS device 10.